The present invention relates to a semiconductor integrated circuit device and the art of manufacturing the same; and, more specifically, the invention relates to improvements applicable to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
The memory cells of a DRAM are arranged at the cross points of a plurality of word lines and a plurality of bit lines all, of which are arranged in the form of a matrix over the principal surface of a semiconductor substrate, and each of the memory cells includes one memory cell selecting MISFET and one information storing capacitive element (capacitor) which is connected in series with the memory cell selecting MISFET. The memory cell selecting MISFET mainly includes a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions which constitute a source and a drain. The bit line is arranged above the memory cell selecting MISFET, and is electrically connected to either one of the source and the drain. The information storing capacitive element is similarly arranged above the memory cell selecting MISFET, and is electrically connected to the other of the source and the drain.
As is known, recent types of DRAMs have adopted a so-called stacked capacitor structure in which information storing capacitive elements are arranged above memory cell selecting MISFETs to compensate for a decrease in the charge storage quantity per information storing capacitive element due to the scaling of memory cells. DRAMs which adopt this stacked capacitor structure are divided into two kinds, a capacitor under bitline (CUB) structure in which information storing capacitive elements are arranged below bit lines and a capacitor over bitline (COB) structure in which information storing capacitive elements are arranged above bit lines.
In the above-described two kinds of stacked capacitor structures, as compared with the CUB structure, the COB structure in which information storing capacitive elements are arranged above bit lines is suited to the scaling of memory cells. This is because, if the charge storage quantity of a scaled information storing capacitive element is to be increased, it is necessary to three-dimensionally design the structure of the information storing capacitive element and increase the surface area thereof, but in the case of the CUB structure in which bit lines are arranged above information storing capacitive elements, contact holes for connecting the bit lines and the memory cell selecting MISFETs become extremely large in aspect ratio and the contact holes become difficult to open.
In the case of recent large-capacity DRAMs such as 64- or 256-Mbit DRAMs, it has become difficult to ensure the required charge storage quantity merely by three-dimensionally forming information storing capacitive elements and increasing the surface areas thereof, and in addition to the three-dimensional formation of the capacitive elements, consideration has been given to the use of a capacitive insulating film formed of a high dielectric material such as Ta.sub.2 O.sub.5 (tantalum oxide), (Ba, Sr)TiO.sub.3 (barium strontium titanate; hereinafter referred to as BST) or SrTiO.sub.3 (strontium titanate; hereinafter referred to as STO). DRAMs using a capacitive insulating film formed of such a high dielectric material are described in, for example, Japanese Patent Laid-Open No. 222469/1989 and U.S. Pat. No. 5,383,088.
Furthermore, in the field of the above-noted 64-to-256-Mbit DRAMs, it has been considered inevitable to use a metal material which is lower in resistance than a polycrystalline silicon film, for the material of word lines and bit lines as a countermeasure for signal delay due to an increase in chip size, or to use the silicidation technique of forming a high melting-point metal silicide layer such as TiSi.sub.2 (titanium silicide) or CoSi.sub.2 (cobalt silicide) over the surfaces of the sources and drains of MISFETs which constitute peripheral circuits, such as sense amplifiers and word drivers, which are required to perform high-speed operation, as a countermeasure for avoiding an increase in resistance due to the scaling of contact holes for connecting interconnect lines and the sources and drains of the MISFETs. This silicidation technique is described in, for example, Japanese Patent Laid-Open Nos. 29240/1994 and 181212/1996.